1. Related Applications
This application is related to U.S. patent application Ser. No. 08/189,139, entitled "Dual Bus Concurrent Multi-Channel Direct Memory Access Controller and Method", Ser. No. 08/189,132, entitled "Multiple Register Set Direct Memory Access Channel Architecture", and Ser. No. 08/189,131, entitled "Direct Memory Access Channel Architecture and Method for Reception of Network Information", each of which is assigned to the assignee of the present invention and filed concurrently herewith.
2. Field of the Invention
The present invention relates to digital computer system architecture. More particularly, the present invention relates to a computer architecture in which multiple processing units share a common memory bus and support real-time applications.
3. Description of Related Art
Until recently, telecommunications and computing were considered to be entirely separate disciplines. Telecommunications was analog and done in real-time whereas computing was digital and performed at a rate determined by the processing speed of a computer. Today, such technologies as speech processing, sound processing, electronic facsimile and image processing have blurred these lines. In the coming years, computing and telecommunications will become almost indistinguishable in a race to support a broad range of new multimedia (i.e., voice, video and traditional data) applications. These applications are made possible by emerging digital-processing technologies, which include: compressed audio (both high fidelity audio and speed), high resolution still images, video, and high speed signal transmission such as by means of modem or facsimile exchange. The emerging technologies will allow for collaboration at a distance such as by video conferencing.
Each of these aspects of real-time information processing may require dedicated processors designed for their implementation. However, it is becoming more and more common to use programmable digital signal processors (DSP) available on the market today, such as the AT&T.RTM. DSP3210. DSPs are autonomous processors having their own real-time operating systems. As such, they are ideally suited to real-time audio and image signal processing.
In handling real-time information such as speech recognition and modem functionality, a DSP requires a large amount of bandwidth to memory for processing the sheer volume of data required to effectuate real-time computing. FIG. 1 illustrates a typical computer architecture in which a CPU 10 is coupled to a memory bus 100. The memory bus 100 may also be referred to as the system bus or CPU bus. In any event, it is this bus which couples the system's CPU 10 to the I/O interface 15 and the various components of the memory subsystem. In FIG. 1, the CPU is in communication with a ROM 12 and the main memory subsystem 14 through the memory bus 100. The main memory subsystem 14 usually comprises a memory controller and a large array of dynamic random access memory (DRAM) for supporting operating applications and data for access by the CPU over the memory bus 100. The main memory subsystem is distinguished from mass storage 16 which may comprise hard magnetic disk drives or a CD-ROM which provide for relatively slow access, high volume storage of information. Access times to mass storage are slower in part because of the need to process requests through the I/O interface and the inherently slower nature of mass storage devices. The memory subsystem's DRAM, on the other hand, is semi-conductor memory which provides for fairly quick storage and retrieval for operating applications and which may be fed from the slower mass storage 16 through the I/O interface 15 over the memory bus 100 to meet the requirements of the CPU 10.
In many computer systems, the I/O interface 15 is also a direct memory access (DMA) controller which manages the transfer of data between I/O devices and the main memory subsystem without requiring the CPU to perform that task. The I/O interface 15 may also be used for coupling the computer system to other computer systems over a network such as an Ethernet local area network.
Also shown coupled to the memory bus 100 in FIG. 1 is a digital signal processor (DSP) 20. The logic or controller needed to couple the DSP to the memory bus is not shown. The DSP 20 may be an off-the-shelf DSP such as the AT&T.RTM. DSP3210. Most DSPs include an on-board cache of static random access memory (SRAM) which in the case of the AT&T DSP3210 is an 8-Kbyte SRAM cache. In prior art computer systems, because of the high bandwidth required for real-time processing by a DSP, it has not been possible for the DSP to run off of the computer system's DRAM in the way the CPU 10 utilizes it without adversely affecting the rest of the computer system. Thus, there has been provided a large block of SRAM 24 for use by the DSP 20. This has allowed the memory bus to be relatively free of DSP requests yielding the freedom to process CPU requests and requests from I/O devices or networks through the I/O interface without having to contend for the bandwidth required by the DSP 20.
A significant disadvantage to the prior art computer architecture of FIG. 1 is the requirement of a substantial block of static random access memory 24. SRAMs are significantly more expensive than DRAM which greatly increases the cost of computer systems which incorporate SRAM. One object of the emerging multimedia technologies is to bring these technologies to the mass market in configurations as inexpensive as possible. It is therefore one object of the present invention to provide a computer architecture which incorporates DSP technology for real-time data processing without requiring the inclusion of expensive SRAM to support the DSP.